1. Field of the Invention
The present invention relates to electrically interconnecting via structures and methods of making same in material, such as, semiconductor material. More particularly, the present invention relates to conductive through via structures and processes for making same in electronic device structures, such as in semiconductor wafers, chips, components and the like, and in electronic device carriers for such semiconductor wafers, chips, components and the like.
2. Background and Related Art
In the packaging of electronic devices, such as, semiconductor chips or wafers, device carriers are used to interconnect the devices. Where electronic devices are connected to another level of packaging, the carriers typically require conductive vias extending through the carrier to connect the devices to the next level of packaging.
Electronic device carriers may be fabricated from a variety of different materials, such as, glass, ceramic, organic and semiconductor materials or combination of these and other materials in single or multiple layers.
Electronic device carriers made of semiconductor material, such as, silicon, offer a number of advantages in packaging, such as ease of manufacturing and reliability. One of the difficulties with fabricating conductive vias in carriers, such as silicon, is forming vias that are reliable. In this regard, a number of processing factors and limitations act to create difficulties in achieving reliable conductive through vias.
The typical prior art approach to creating conductive vias in semiconductor carriers, such as silicon, use what might be called a “vias first” approach. The general steps in such an approach are etching the vias, forming insulation layers on the via walls and metallization. When a “blind via” approach is used, the vias are not etched through the wafer layer so that a “through via” is rendered only after the carrier is suitably thinned to expose the via bottoms. An example of such an approach may be seen in U.S. Pat. No. 5,998,292.
There are, however, a number of difficulties with this type of approach. One difficulty is that this approach requires that the insulation and subsequent metallization must typically completely fill each via, if any wiring layers are to be added to the top. In addition, completely filling vias in silicon carriers without leaving voids is problematic, particularly in deep vias. Formation of the insulation layers on the via walls is typically done through thermal oxidation. Filling the via with metal after thermally oxidized passivation effectively initiates the back end of line (BEOL) process. On the other hand, where passivation is accomplished by chemical vapor deposition (CVD) after BEOL processing, it is difficult to completely cover the walls with oxide in the lower levels of deep vias, particularly around the region of generally intersecting vertical and bottom surfaces, since CVD is not fully conformal. As a result, any exposed silicon may result in metal contamination of the silicon carrier during subsequent front end of line (FEOL) thermal processing steps where the via has been filled with metal, such as Cu.
Moreover, filling insulated vias in the silicon carrier with metal using standard methods, such as plating, for large aspect ratios (e.g. greater than 10:1) tends to lead to plating inclusions and voids which may trap solution causing them to rupture in high-temperature FEOL processing steps.
Another difficulty with creating vias in silicon carriers is that the anisotropic etch of the vias varies both in rate and in maximum depth attainable inversely with size of the feature to be etched. Thus, the ultimate thickness of the carrier is somewhat determined by the feature size. Larger features, such as vias and silicon, can be etched deeper, but they also require thicker metallization to completely fill them. Depending upon the CTE mismatch of metal used to fill the vias and silicon, large stresses can build up in the vias leading to plastic deformation of the metal and/or cracking of the silicon carrier, both of which result in reliability problems.